<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>To see the actual file transmitted to Xilinx, please click <A HREF="./usage_statistics_webtalk.xml">here</A>.<BR><BR><HR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
  <TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>2708876</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Wed Feb 26 09:36:13 2025</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>Vivado v2019.2 (64-bit)</TD>
  <TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>4ea7dce6a5fb4333b70924fda5c0c48c</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>7</TD>
  <TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>a423f69f8fde50ee991ac35ac7c3bb42</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>a423f69f8fde50ee991ac35ac7c3bb42</TD>
  <TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>TRUE</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>xc7a100t</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>artix7</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>csg324</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>-1</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>Vivado</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>12th Gen Intel(R) Core(TM) i7-1260P</TD>
  <TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>2496 MHz</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Windows Server 2016 or Windows 10</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release  (build 9200)</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>16.000 GB</TD>
  <TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
<TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>gui_handlers</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>abstractcombinedpanel_remove_selected_elements=2</TD>
   <TD>addsrcwizard_specify_or_create_constraint_files=1</TD>
   <TD>addsrcwizard_specify_simulation_specific_hdl_files=1</TD>
   <TD>basedialog_cancel=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>basedialog_ok=41</TD>
   <TD>basedialog_yes=5</TD>
   <TD>closeplanner_yes=1</TD>
   <TD>cmdmsgdialog_messages=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>cmdmsgdialog_ok=8</TD>
   <TD>constraintschooserpanel_add_files=1</TD>
   <TD>constraintschooserpanel_copy_constraints_files_into_project=1</TD>
   <TD>createsrcfiledialog_file_name=15</TD>
</TR><TR ALIGN='LEFT'>   <TD>createsrcfiledialog_file_type=13</TD>
   <TD>filesetpanel_file_set_panel_tree=180</TD>
   <TD>filesetpanel_messages=1</TD>
   <TD>flownavigatortreepanel_flow_navigator_tree=49</TD>
</TR><TR ALIGN='LEFT'>   <TD>fpgachooser_fpga_table=2</TD>
   <TD>gettingstartedview_create_new_project=1</TD>
   <TD>gettingstartedview_open_project=3</TD>
   <TD>hcodeeditor_search_text_combo_box=4</TD>
</TR><TR ALIGN='LEFT'>   <TD>msgview_information_messages=1</TD>
   <TD>newprojectwizard_do_not_specify_sources_at_this_time=1</TD>
   <TD>pacommandnames_add_sources=14</TD>
   <TD>pacommandnames_auto_connect_target=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>paviews_code=13</TD>
   <TD>paviews_device=1</TD>
   <TD>paviews_project_summary=5</TD>
   <TD>paviews_schematic=4</TD>
</TR><TR ALIGN='LEFT'>   <TD>programfpgadialog_program=4</TD>
   <TD>projectnamechooser_choose_project_location=2</TD>
   <TD>projectnamechooser_project_name=1</TD>
   <TD>projecttab_reload=7</TD>
</TR><TR ALIGN='LEFT'>   <TD>saveprojectutils_save=3</TD>
   <TD>srcchooserpanel_add_hdl_and_netlist_files_to_your_project=2</TD>
   <TD>srcchooserpanel_add_or_create_source_file=2</TD>
   <TD>srcchooserpanel_create_file=15</TD>
</TR><TR ALIGN='LEFT'>   <TD>srcchoosertable_src_chooser_table=9</TD>
   <TD>taskbanner_close=1</TD>
   <TD>touchpointsurveydialog_no=1</TD>
</TR>  </TABLE>
  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>java_command_handlers</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>addsources=14</TD>
   <TD>autoconnecttarget=1</TD>
   <TD>fliptoviewtaskrtlanalysis=1</TD>
   <TD>launchprogramfpga=4</TD>
</TR><TR ALIGN='LEFT'>   <TD>newproject=1</TD>
   <TD>openhardwaremanager=6</TD>
   <TD>openproject=3</TD>
   <TD>openrecenttarget=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>programdevice=4</TD>
   <TD>runbitgen=8</TD>
   <TD>runschematic=7</TD>
   <TD>runsynthesis=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>savefileproxyhandler=2</TD>
   <TD>showview=5</TD>
   <TD>viewtaskimplementation=1</TD>
   <TD>viewtaskprojectmanager=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>viewtaskrtlanalysis=2</TD>
</TR>  </TABLE>
</TR><TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>other_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>guimode=4</TD>
</TR>  </TABLE>
  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>project_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>constraintsetcount=1</TD>
   <TD>core_container=false</TD>
   <TD>currentimplrun=impl_1</TD>
   <TD>currentsynthesisrun=synth_1</TD>
</TR><TR ALIGN='LEFT'>   <TD>default_library=xil_defaultlib</TD>
   <TD>designmode=RTL</TD>
   <TD>export_simulation_activehdl=0</TD>
   <TD>export_simulation_ies=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_modelsim=0</TD>
   <TD>export_simulation_questa=0</TD>
   <TD>export_simulation_riviera=0</TD>
   <TD>export_simulation_vcs=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_xsim=0</TD>
   <TD>implstrategy=Vivado Implementation Defaults</TD>
   <TD>launch_simulation_activehdl=0</TD>
   <TD>launch_simulation_ies=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_modelsim=0</TD>
   <TD>launch_simulation_questa=0</TD>
   <TD>launch_simulation_riviera=0</TD>
   <TD>launch_simulation_vcs=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_xsim=0</TD>
   <TD>simulator_language=Mixed</TD>
   <TD>srcsetcount=10</TD>
   <TD>synthesisstrategy=Vivado Synthesis Defaults</TD>
</TR><TR ALIGN='LEFT'>   <TD>target_language=Verilog</TD>
   <TD>target_simulator=XSim</TD>
   <TD>totalimplruns=1</TD>
   <TD>totalsynthesisruns=1</TD>
</TR>  </TABLE>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>unisim_transformation</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>post_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg=1</TD>
    <TD>carry4=15</TD>
    <TD>fdre=20</TD>
    <TD>gnd=3</TD>
</TR><TR ALIGN='LEFT'>    <TD>ibuf=17</TD>
    <TD>lut1=1</TD>
    <TD>lut2=1</TD>
    <TD>lut3=39</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut4=7</TD>
    <TD>lut5=15</TD>
    <TD>lut6=11</TD>
    <TD>obuf=31</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcc=2</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pre_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg=1</TD>
    <TD>carry4=15</TD>
    <TD>fdre=20</TD>
    <TD>gnd=3</TD>
</TR><TR ALIGN='LEFT'>    <TD>ibuf=17</TD>
    <TD>lut1=1</TD>
    <TD>lut2=1</TD>
    <TD>lut3=39</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut4=7</TD>
    <TD>lut5=15</TD>
    <TD>lut6=11</TD>
    <TD>obuf=31</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcc=2</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>phys_opt_design_post_place</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-aggressive_hold_fix=default::[not_specified]</TD>
    <TD>-bram_register_opt=default::[not_specified]</TD>
    <TD>-clock_opt=default::[not_specified]</TD>
    <TD>-critical_cell_opt=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-critical_pin_opt=default::[not_specified]</TD>
    <TD>-directive=default::[not_specified]</TD>
    <TD>-dsp_register_opt=default::[not_specified]</TD>
    <TD>-effort_level=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-fanout_opt=default::[not_specified]</TD>
    <TD>-hold_fix=default::[not_specified]</TD>
    <TD>-insert_negative_edge_ffs=default::[not_specified]</TD>
    <TD>-multi_clock_opt=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-placement_opt=default::[not_specified]</TD>
    <TD>-restruct_opt=default::[not_specified]</TD>
    <TD>-retime=default::[not_specified]</TD>
    <TD>-rewire=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-shift_register_opt=default::[not_specified]</TD>
    <TD>-uram_register_opt=default::[not_specified]</TD>
    <TD>-verbose=default::[not_specified]</TD>
    <TD>-vhfn=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_drc</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
    <TD>-checks=default::[not_specified]</TD>
    <TD>-fail_on=default::[not_specified]</TD>
    <TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-format=default::[not_specified]</TD>
    <TD>-internal=default::[not_specified]</TD>
    <TD>-internal_only=default::[not_specified]</TD>
    <TD>-messages=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-name=default::[not_specified]</TD>
    <TD>-no_waivers=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
    <TD>-ruledecks=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-upgrade_cw=default::[not_specified]</TD>
    <TD>-waived=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>cfgbvs-1=1</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_methodology</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
    <TD>-checks=default::[not_specified]</TD>
    <TD>-fail_on=default::[not_specified]</TD>
    <TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-format=default::[not_specified]</TD>
    <TD>-messages=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-slack_lesser_than=default::[not_specified]</TD>
    <TD>-waived=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>timing-18=15</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_power</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-advisory=default::[not_specified]</TD>
    <TD>-append=default::[not_specified]</TD>
    <TD>-file=[specified]</TD>
    <TD>-format=default::text</TD>
</TR><TR ALIGN='LEFT'>    <TD>-hier=default::power</TD>
    <TD>-hierarchical_depth=default::4</TD>
    <TD>-l=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-no_propagation=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
    <TD>-rpx=[specified]</TD>
    <TD>-verbose=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-vid=default::[not_specified]</TD>
    <TD>-xpe=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>airflow=250 (LFM)</TD>
    <TD>ambient_temp=25.0 (C)</TD>
    <TD>bi-dir_toggle=12.500000</TD>
    <TD>bidir_output_enable=1.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>board_layers=12to15 (12 to 15 Layers)</TD>
    <TD>board_selection=medium (10&quot;x10&quot;)</TD>
    <TD>clocks=0.000545</TD>
    <TD>confidence_level_clock_activity=High</TD>
</TR><TR ALIGN='LEFT'>    <TD>confidence_level_design_state=High</TD>
    <TD>confidence_level_device_models=High</TD>
    <TD>confidence_level_internal_activity=Medium</TD>
    <TD>confidence_level_io_activity=Low</TD>
</TR><TR ALIGN='LEFT'>    <TD>confidence_level_overall=Low</TD>
    <TD>customer=TBD</TD>
    <TD>customer_class=TBD</TD>
    <TD>devstatic=0.097143</TD>
</TR><TR ALIGN='LEFT'>    <TD>die=xc7a100tcsg324-1</TD>
    <TD>dsp_output_toggle=12.500000</TD>
    <TD>dynamic=0.025417</TD>
    <TD>effective_thetaja=4.6</TD>
</TR><TR ALIGN='LEFT'>    <TD>enable_probability=0.990000</TD>
    <TD>family=artix7</TD>
    <TD>ff_toggle=12.500000</TD>
    <TD>flow_state=routed</TD>
</TR><TR ALIGN='LEFT'>    <TD>heatsink=medium (Medium Profile)</TD>
    <TD>i/o=0.024149</TD>
    <TD>input_toggle=12.500000</TD>
    <TD>junction_temp=25.6 (C)</TD>
</TR><TR ALIGN='LEFT'>    <TD>logic=0.000276</TD>
    <TD>mgtavcc_dynamic_current=0.000000</TD>
    <TD>mgtavcc_static_current=0.000000</TD>
    <TD>mgtavcc_total_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>mgtavcc_voltage=1.000000</TD>
    <TD>mgtavtt_dynamic_current=0.000000</TD>
    <TD>mgtavtt_static_current=0.000000</TD>
    <TD>mgtavtt_total_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>mgtavtt_voltage=1.200000</TD>
    <TD>netlist_net_matched=NA</TD>
    <TD>off-chip_power=0.000000</TD>
    <TD>on-chip_power=0.122560</TD>
</TR><TR ALIGN='LEFT'>    <TD>output_enable=1.000000</TD>
    <TD>output_load=5.000000</TD>
    <TD>output_toggle=12.500000</TD>
    <TD>package=csg324</TD>
</TR><TR ALIGN='LEFT'>    <TD>pct_clock_constrained=1.000000</TD>
    <TD>pct_inputs_defined=5</TD>
    <TD>platform=nt64</TD>
    <TD>process=typical</TD>
</TR><TR ALIGN='LEFT'>    <TD>ram_enable=50.000000</TD>
    <TD>ram_write=50.000000</TD>
    <TD>read_saif=False</TD>
    <TD>set/reset_probability=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>signal_rate=False</TD>
    <TD>signals=0.000447</TD>
    <TD>simulation_file=None</TD>
    <TD>speedgrade=-1</TD>
</TR><TR ALIGN='LEFT'>    <TD>static_prob=False</TD>
    <TD>temp_grade=commercial</TD>
    <TD>thetajb=5.7 (C/W)</TD>
    <TD>thetasa=4.6 (C/W)</TD>
</TR><TR ALIGN='LEFT'>    <TD>toggle_rate=False</TD>
    <TD>user_board_temp=25.0 (C)</TD>
    <TD>user_effective_thetaja=4.6</TD>
    <TD>user_junc_temp=25.6 (C)</TD>
</TR><TR ALIGN='LEFT'>    <TD>user_thetajb=5.7 (C/W)</TD>
    <TD>user_thetasa=4.6 (C/W)</TD>
    <TD>vccadc_dynamic_current=0.000000</TD>
    <TD>vccadc_static_current=0.020000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccadc_total_current=0.020000</TD>
    <TD>vccadc_voltage=1.800000</TD>
    <TD>vccaux_dynamic_current=0.000880</TD>
    <TD>vccaux_io_dynamic_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccaux_io_static_current=0.000000</TD>
    <TD>vccaux_io_total_current=0.000000</TD>
    <TD>vccaux_io_voltage=1.800000</TD>
    <TD>vccaux_static_current=0.018144</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccaux_total_current=0.019025</TD>
    <TD>vccaux_voltage=1.800000</TD>
    <TD>vccbram_dynamic_current=0.000000</TD>
    <TD>vccbram_static_current=0.000246</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccbram_total_current=0.000246</TD>
    <TD>vccbram_voltage=1.000000</TD>
    <TD>vccint_dynamic_current=0.001396</TD>
    <TD>vccint_static_current=0.015037</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccint_total_current=0.016433</TD>
    <TD>vccint_voltage=1.000000</TD>
    <TD>vcco12_dynamic_current=0.000000</TD>
    <TD>vcco12_static_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco12_total_current=0.000000</TD>
    <TD>vcco12_voltage=1.200000</TD>
    <TD>vcco135_dynamic_current=0.000000</TD>
    <TD>vcco135_static_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco135_total_current=0.000000</TD>
    <TD>vcco135_voltage=1.350000</TD>
    <TD>vcco15_dynamic_current=0.000000</TD>
    <TD>vcco15_static_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco15_total_current=0.000000</TD>
    <TD>vcco15_voltage=1.500000</TD>
    <TD>vcco18_dynamic_current=0.000000</TD>
    <TD>vcco18_static_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco18_total_current=0.000000</TD>
    <TD>vcco18_voltage=1.800000</TD>
    <TD>vcco25_dynamic_current=0.000000</TD>
    <TD>vcco25_static_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco25_total_current=0.000000</TD>
    <TD>vcco25_voltage=2.500000</TD>
    <TD>vcco33_dynamic_current=0.006799</TD>
    <TD>vcco33_static_current=0.004000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco33_total_current=0.010799</TD>
    <TD>vcco33_voltage=3.300000</TD>
    <TD>version=2019.2</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_utilization</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clocking</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufgctrl_available=32</TD>
    <TD>bufgctrl_fixed=0</TD>
    <TD>bufgctrl_used=1</TD>
    <TD>bufgctrl_util_percentage=3.13</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufhce_available=96</TD>
    <TD>bufhce_fixed=0</TD>
    <TD>bufhce_used=0</TD>
    <TD>bufhce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufio_available=24</TD>
    <TD>bufio_fixed=0</TD>
    <TD>bufio_used=0</TD>
    <TD>bufio_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufmrce_available=12</TD>
    <TD>bufmrce_fixed=0</TD>
    <TD>bufmrce_used=0</TD>
    <TD>bufmrce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufr_available=24</TD>
    <TD>bufr_fixed=0</TD>
    <TD>bufr_used=0</TD>
    <TD>bufr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>mmcme2_adv_available=6</TD>
    <TD>mmcme2_adv_fixed=0</TD>
    <TD>mmcme2_adv_used=0</TD>
    <TD>mmcme2_adv_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>plle2_adv_available=6</TD>
    <TD>plle2_adv_fixed=0</TD>
    <TD>plle2_adv_used=0</TD>
    <TD>plle2_adv_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dsp</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>dsps_available=240</TD>
    <TD>dsps_fixed=0</TD>
    <TD>dsps_used=0</TD>
    <TD>dsps_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>io_standard</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>blvds_25=0</TD>
    <TD>diff_hstl_i=0</TD>
    <TD>diff_hstl_i_18=0</TD>
    <TD>diff_hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_hstl_ii_18=0</TD>
    <TD>diff_hsul_12=0</TD>
    <TD>diff_mobile_ddr=0</TD>
    <TD>diff_sstl135=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl135_r=0</TD>
    <TD>diff_sstl15=0</TD>
    <TD>diff_sstl15_r=0</TD>
    <TD>diff_sstl18_i=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl18_ii=0</TD>
    <TD>hstl_i=0</TD>
    <TD>hstl_i_18=0</TD>
    <TD>hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>hstl_ii_18=0</TD>
    <TD>hsul_12=0</TD>
    <TD>lvcmos12=0</TD>
    <TD>lvcmos15=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvcmos18=1</TD>
    <TD>lvcmos25=0</TD>
    <TD>lvcmos33=1</TD>
    <TD>lvds_25=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvttl=0</TD>
    <TD>mini_lvds_25=0</TD>
    <TD>mobile_ddr=0</TD>
    <TD>pci33_3=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>ppds_25=0</TD>
    <TD>rsds_25=0</TD>
    <TD>sstl135=0</TD>
    <TD>sstl135_r=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>sstl15=0</TD>
    <TD>sstl15_r=0</TD>
    <TD>sstl18_i=0</TD>
    <TD>sstl18_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>tmds_33=0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>memory</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>block_ram_tile_available=135</TD>
    <TD>block_ram_tile_fixed=0</TD>
    <TD>block_ram_tile_used=0</TD>
    <TD>block_ram_tile_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb18_available=270</TD>
    <TD>ramb18_fixed=0</TD>
    <TD>ramb18_used=0</TD>
    <TD>ramb18_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb36_fifo_available=135</TD>
    <TD>ramb36_fifo_fixed=0</TD>
    <TD>ramb36_fifo_used=0</TD>
    <TD>ramb36_fifo_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>primitives</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg_functional_category=Clock</TD>
    <TD>bufg_used=1</TD>
    <TD>carry4_functional_category=CarryLogic</TD>
    <TD>carry4_used=15</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdre_functional_category=Flop &amp; Latch</TD>
    <TD>fdre_used=20</TD>
    <TD>ibuf_functional_category=IO</TD>
    <TD>ibuf_used=17</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut1_functional_category=LUT</TD>
    <TD>lut1_used=1</TD>
    <TD>lut2_functional_category=LUT</TD>
    <TD>lut2_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut3_functional_category=LUT</TD>
    <TD>lut3_used=39</TD>
    <TD>lut4_functional_category=LUT</TD>
    <TD>lut4_used=7</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut5_functional_category=LUT</TD>
    <TD>lut5_used=15</TD>
    <TD>lut6_functional_category=LUT</TD>
    <TD>lut6_used=11</TD>
</TR><TR ALIGN='LEFT'>    <TD>obuf_functional_category=IO</TD>
    <TD>obuf_used=31</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>slice_logic</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>f7_muxes_available=31700</TD>
    <TD>f7_muxes_fixed=0</TD>
    <TD>f7_muxes_used=0</TD>
    <TD>f7_muxes_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>f8_muxes_available=15850</TD>
    <TD>f8_muxes_fixed=0</TD>
    <TD>f8_muxes_used=0</TD>
    <TD>f8_muxes_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_available=63400</TD>
    <TD>lut_as_logic_fixed=0</TD>
    <TD>lut_as_logic_used=66</TD>
    <TD>lut_as_logic_util_percentage=0.10</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_available=19000</TD>
    <TD>lut_as_memory_fixed=0</TD>
    <TD>lut_as_memory_used=0</TD>
    <TD>lut_as_memory_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_flip_flop_available=126800</TD>
    <TD>register_as_flip_flop_fixed=0</TD>
    <TD>register_as_flip_flop_used=20</TD>
    <TD>register_as_flip_flop_util_percentage=0.02</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_latch_available=126800</TD>
    <TD>register_as_latch_fixed=0</TD>
    <TD>register_as_latch_used=0</TD>
    <TD>register_as_latch_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_luts_available=63400</TD>
    <TD>slice_luts_fixed=0</TD>
    <TD>slice_luts_used=66</TD>
    <TD>slice_luts_util_percentage=0.10</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_available=126800</TD>
    <TD>slice_registers_fixed=0</TD>
    <TD>slice_registers_used=20</TD>
    <TD>slice_registers_util_percentage=0.02</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_distributed_ram_fixed=0</TD>
    <TD>lut_as_distributed_ram_used=0</TD>
    <TD>lut_as_logic_available=63400</TD>
    <TD>lut_as_logic_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_used=66</TD>
    <TD>lut_as_logic_util_percentage=0.10</TD>
    <TD>lut_as_memory_available=19000</TD>
    <TD>lut_as_memory_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_used=0</TD>
    <TD>lut_as_memory_util_percentage=0.00</TD>
    <TD>lut_as_shift_register_fixed=0</TD>
    <TD>lut_as_shift_register_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_driven_from_outside_the_slice_fixed=0</TD>
    <TD>register_driven_from_outside_the_slice_used=0</TD>
    <TD>register_driven_from_within_the_slice_fixed=0</TD>
    <TD>register_driven_from_within_the_slice_used=20</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_available=15850</TD>
    <TD>slice_fixed=0</TD>
    <TD>slice_registers_available=126800</TD>
    <TD>slice_registers_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_used=20</TD>
    <TD>slice_registers_util_percentage=0.02</TD>
    <TD>slice_used=28</TD>
    <TD>slice_util_percentage=0.18</TD>
</TR><TR ALIGN='LEFT'>    <TD>slicel_fixed=0</TD>
    <TD>slicel_used=20</TD>
    <TD>slicem_fixed=0</TD>
    <TD>slicem_used=8</TD>
</TR><TR ALIGN='LEFT'>    <TD>unique_control_sets_available=15850</TD>
    <TD>unique_control_sets_fixed=15850</TD>
    <TD>unique_control_sets_used=1</TD>
    <TD>unique_control_sets_util_percentage=&lt;0.01</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o5_and_o6_fixed=&lt;0.01</TD>
    <TD>using_o5_and_o6_used=8</TD>
    <TD>using_o5_output_only_fixed=8</TD>
    <TD>using_o5_output_only_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o6_output_only_fixed=0</TD>
    <TD>using_o6_output_only_used=58</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>specific_feature</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bscane2_available=4</TD>
    <TD>bscane2_fixed=0</TD>
    <TD>bscane2_used=0</TD>
    <TD>bscane2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>capturee2_available=1</TD>
    <TD>capturee2_fixed=0</TD>
    <TD>capturee2_used=0</TD>
    <TD>capturee2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>dna_port_available=1</TD>
    <TD>dna_port_fixed=0</TD>
    <TD>dna_port_used=0</TD>
    <TD>dna_port_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>efuse_usr_available=1</TD>
    <TD>efuse_usr_fixed=0</TD>
    <TD>efuse_usr_used=0</TD>
    <TD>efuse_usr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>frame_ecce2_available=1</TD>
    <TD>frame_ecce2_fixed=0</TD>
    <TD>frame_ecce2_used=0</TD>
    <TD>frame_ecce2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>icape2_available=2</TD>
    <TD>icape2_fixed=0</TD>
    <TD>icape2_used=0</TD>
    <TD>icape2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcie_2_1_available=1</TD>
    <TD>pcie_2_1_fixed=0</TD>
    <TD>pcie_2_1_used=0</TD>
    <TD>pcie_2_1_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>startupe2_available=1</TD>
    <TD>startupe2_fixed=0</TD>
    <TD>startupe2_used=0</TD>
    <TD>startupe2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>xadc_available=1</TD>
    <TD>xadc_fixed=0</TD>
    <TD>xadc_used=0</TD>
    <TD>xadc_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>synthesis</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-assert=default::[not_specified]</TD>
    <TD>-bufg=default::12</TD>
    <TD>-cascade_dsp=default::auto</TD>
    <TD>-constrset=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-control_set_opt_threshold=default::auto</TD>
    <TD>-directive=default::default</TD>
    <TD>-fanout_limit=default::10000</TD>
    <TD>-flatten_hierarchy=default::rebuilt</TD>
</TR><TR ALIGN='LEFT'>    <TD>-fsm_extraction=default::auto</TD>
    <TD>-gated_clock_conversion=default::off</TD>
    <TD>-generic=default::[not_specified]</TD>
    <TD>-include_dirs=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-keep_equivalent_registers=default::[not_specified]</TD>
    <TD>-max_bram=default::-1</TD>
    <TD>-max_bram_cascade_height=default::-1</TD>
    <TD>-max_dsp=default::-1</TD>
</TR><TR ALIGN='LEFT'>    <TD>-max_uram=default::-1</TD>
    <TD>-max_uram_cascade_height=default::-1</TD>
    <TD>-mode=default::default</TD>
    <TD>-name=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-no_lc=default::[not_specified]</TD>
    <TD>-no_srlextract=default::[not_specified]</TD>
    <TD>-no_timing_driven=default::[not_specified]</TD>
    <TD>-part=xc7a100tcsg324-1</TD>
</TR><TR ALIGN='LEFT'>    <TD>-resource_sharing=default::auto</TD>
    <TD>-retiming=default::[not_specified]</TD>
    <TD>-rtl=default::[not_specified]</TD>
    <TD>-rtl_skip_constraints=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-rtl_skip_ip=default::[not_specified]</TD>
    <TD>-seu_protect=default::none</TD>
    <TD>-sfcu=default::[not_specified]</TD>
    <TD>-shreg_min_size=default::3</TD>
</TR><TR ALIGN='LEFT'>    <TD>-top=ALU_Top</TD>
    <TD>-verilog_define=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>elapsed=00:00:19s</TD>
    <TD>hls_ip=0</TD>
    <TD>memory_gain=694.312MB</TD>
    <TD>memory_peak=1102.113MB</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
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